Many modern integrated circuits are fabricated utilizing the "Local Oxidation of Silicon" (LOCOS) process. The LOCOS process involves the formation of a patterned layer, usually comprising silicon nitride, upon a silicon substrate. The exposed portions of the silicon substrate are subsequently oxidized to form silicon dioxide regions which are called field oxides.
An alternative to the LOCOS process is the poly-buffered LOCOS process ("PBL"). In the PBL process, a layer of stress relieving material, such as polysilicon is formed beneath the silicon nitride before oxidation of the silicon substrate. The polysilicon helps to absorb stresses generated during the oxidation process.
As integrated circuit geometries become smaller the spacing between adjacent portions of patterned silicon nitride (in the LOCOS process) or patterned silicon nitride and polysilicon (in the PBL process) has become smaller. For example, in FIG. 1, reference numeral 11 denotes a substrate which may be typically silicon. A thin oxide layer 13 may be formed on top of substrate 11. Reference numerals 15, 17 and 19 denote portions of a patterned polysilicon layer. Reference numerals 21, 23 and 25 denote portions of a patterned silicon nitride layer which is formed on top of respective portions 15, 17 and 19 of the patterned polysilicon layer.
It should be noted that the spacing between the patterned polysilicon--silicon nitride may vary. For example, the spacing denoted by d.sub.1 (between polysilicon-silicon nitride elements 19-25 and 17-23) is smaller than the spacing denoted by d.sub.2 (between polysilicon-silicon nitride elements 17-23 and 15-21). If spacing d.sub.1 is significantly smaller than spacing d.sub.2, the field oxide formed within spacing d.sub.1 may be significantly shorter than the field oxide formed within spacing d.sub.2. For example, in FIG. 1, the height of field oxide 29 which is located in spacing d.sub.1 is less than the height of field oxide 27 which is located in spacing d.sub.2. In other words, upper surface 33 of field oxide 29 is lower (i.e., closer to surface 33 of substrate 11) than upper surface 31 of field oxide 27.
However, it is desirable that most of the field oxides in a particular integrated circuit have the same or nearly the same height (as measured from the surface of the substrate). Differences in height, such as illustrated in FIG. 1, may cause complications in subsequent processing steps such as planarization or via etching. Furthermore, field oxides which are too short may not adequately separate overlying runners from the substrate and thus may permit the formation of parasitic transistors.
Those concerned with the development of integrated circuit technology have sought methods and structures which may alleviate the above-mentioned problem.